Recently, in an integrated circuit, silicon on insulator (SOI) substrate has been used instead of a silicon substrate to decrease a parasitic capacitance between a drain and a substrate in a transistor, thus enhancing a performance of a semiconductor integrated circuit.
However, with a continuous scaling down of a semiconductor device size, a size of a single transistor has gradually reached a physical limit thereof, and therefore a CMOS device with silicon as a channel material has a lowered mobility, which may not meet a performance improvement of the semiconductor device. In order to solve this problem, conventionally, strained silicon techniques are adopted to improve the mobility of silicon, or other materials with higher mobility are used to replace the silicon as the channel material for the device, among which Ge has obtained more attention because of its high hole carrier mobility. The hole carrier mobility of Ge or SiGe with high Ge content is much higher than that of the silicon, and consequently may be used for fabricating a PMOS device by using a CMOS process.
Therefore, conventionally, an insulation layer, for example, a SiO2 layer, has been used in a Ge device to improve the performance of the semiconductor device. For example, a Ge layer is formed directly on the insulation layer as the channel layer.
Conventionally, an interface between the insulation layer and the Ge layer has a poor interface state, which may cause serious scattering and leakage and consequently may influence the performance of the device.